IBM said Thursday it has built the first sub-1 nanometer chip technology, a 0.7 nm (7 angstrom) node it announced from its Yorktown Heights, New York research arm. The headline number: nearly 100 billion transistors on a chip the size of a fingernail, roughly double the density of the 2 nm chip IBM showed off in 2021.
What nanostack actually does
The trick here isn't smaller transistors. It's stacking them. IBM's new architecture, which it calls nanostack, vertically stacks and staggers transistors using 3D sequential integration. The company describes it as the first three-dimensional, nanosheet-based design, building on the nanosheet work that got IBM to 2 nm in the first place.
What makes the stacking interesting, and not just a packing exercise, is that each layer can use a different mix of materials. So you can tune one transistor's performance and power independently of the one sitting on top of it. That's the part worth paying attention to.
IBM also says it physically validated the thing, not just modeled it: ultra-thin dielectric bonding, dual-channel engineering, a working CMOS inverter. In other words, it switches.
The numbers, and what they're measured against
IBM projects up to 50 percent more performance, or up to 70 percent better energy efficiency, versus its own 2 nm node. Note the "or." You get one or the other depending on how you tune it, not both at once, which is standard for these comparisons but easy to skim past.
And the baseline is IBM's 2 nm chip from 2021, a research device that, like IBM's earlier 7 nm and 5 nm announcements, never shipped as a product. IBM sold its fabs to GlobalFoundries back in 2014 and now develops process technology for partners. So "100 billion transistors on a fingernail" is a lab result measured against an earlier lab result. Impressive, but worth keeping in frame.
"We're not just making smaller transistors, we're reinventing how chips are built," said Jay Gambetta, Director of IBM Research. Reinventing is a strong word for stacking, though the independent-materials angle gives the claim more weight than the usual launch-day boilerplate.
SRAM, the part AI people care about
At VLSI 2026, IBM researchers reported the nanostack design delivers 40 percent scaling in SRAM. Denser SRAM matters because AI workloads are starved for on-chip memory bandwidth, and SRAM has been one of the stubborn things that refuses to shrink at the same pace as logic. If the 40 percent holds up outside the lab, that's arguably the more practical result than the transistor count.
So when does any of this ship?
IBM puts production at "as early as the next 5 years," which in semiconductor roadmap language means don't hold your breath. The work happens at the Albany, New York facility, which is slated to get a High NA EUV lithography tool from ASML, the kind of machine you need to actually print features this small.
The next concrete checkpoint is the technical detail IBM presents at VLSI 2026, where the SRAM and nanostack papers land. After that, watch Albany for whether the High NA EUV tool produces working sub-1 nm devices, the real test of whether this leaves the lab.
